power management, asic services and more- F.R.E.S.H Integrated Circuits
F.R.E.S.H Integrated Circuits
MLP Package
RF - Flat Pack

Bringing the Right Product to the Right Place


  • Physical implementation: place & route, timing analysis, extraction, verification and DRC
  • DFT / DFM: testability analysis, test development and manufacturing process analysis
  • Package design: custom package design, thermal analysis and chip / package interface simulation


  • Device qualification: custom qualification programs, stress and life testing
  • Fast / slow device characterization
  • Yield ramp: test data analysis and process tuning


  • Long-standing relationship with TSMC, enabling unparalleled manufacturing services
  • Multiple suppliers to address standard and custom package needs
  • Relationships with both domestic and offshore testing facilities for complete support of your chip requirements

GS1010-EVAL-TLS - Evaluation Board

A complete platform for evaluating GainSpan's wireless system-on-a-chip and embedded software

GainSpan Management System

An optimized software solution for sensor networks

Software Development Kit

The GainSpan GS1010 Software Development Kit (SDK) supports rapid development of hardware and application software for Wi-Fi sensors based on GainSpan's GS1010 ultra-low-power wireless system-ona-chip (SoC).

3rd party development tools for ARM based SoC

  • ECLinPS
  • Low Voltage ECLinPS
  • ECLinPS Lite
  • ECLinPS Lite Translators
  • ECLinPS Plus
  • Low Voltage ECLinPS Lite
  • Phase-Locked Loops
  • Limiting Post Amplifiers
Ethernet Switches & CAM
  • Ethernet Switches
  • Cam

1. Technology and Custom Design

Generally speaking, vision systems are different from cameras and/or imagers. Although vision devices can operate as cameras, their functionality goes quite further. The function of a camera is acquiring (sensing) images. A vision device not only acquires but also processes the image flow in space and time to extract the information contained in such a flow.

A rough description of a Vision System on-Chip is as follows: "A system whose input is a two-dimensional set of analog signals representing a visual flow, which internally converts these signals to the digital domain, and which processes these digital data afterwards". In a conventional vision system, conversion to the digital domain occurs right after the sensors. Hence, all processing is realized in the digital domain. AnaFocus employs a different strategy.

2. Products

Eye-RIS v1.0

This version 1.0 will include an optimized topographical focal-plane ACE-like processor with spatial resolution in the QCIF range. This processor is currently being designed as an improved version of the ACE16k. In this version, digital post-processing will be performed using off-chip components mounted on a small PCB processing module.

AnaFocus Eye-RIS_v1.0 will be accompanied by a complete hardware-software OEM kit. This kit is intended to support application development and will include:

  • The Eye-RIS_v1.0 Software Development Kit (SDK) comprising:
    • A project builder integrating a C compiler, assembler and linker,
    • A source-level debugger,
    • A real-time operating system
    • An image-processing library including basic routines such as:
      • point-to-point operations (arithmetic, binarization, ...),
      • spatial filtering operations (Sobel, Median filter, ...),
      • morphological operations (dilation, erosion, ...),
      • statistical operations (histograms, ...),
      • geometric transformations (rotation, scaling, ...).
  • The Eye-RIS_v1.0 Hardware Development Tools comprising:
    • An Eye-RIS_v1.0 PCB processing module,
    • A host interface PCB including uncommitted FPGA, Flash, SRAM and SDRAM memory, and widely used communication interfaces; and
    • Hardware debugging tools (trace, JTAG, ...) (www.anafocus.com)

Eye-RIS v2.0

The following step in the AnaFocus roadmap is the design of Eye-RIS_v2.0. This version will incorporate on-chip all the structures needed for digital post-processing.

Eye-RIS_v2.0 will be made available as two different products:

  • Eye-RIS_v2.0 FPP (Focal Plane Processor). This will be optimized for applications demanding low-cost ultra-fast, medium-resolution image acquisition and processing with very low-power consumption. Its architecture includes:

    • An ACE-like focal-plane early-processor with QCIF resolution;
    • A 32bit high-performance RISC digital microprocessor for image post-processing and system control;
    • Embedded SRAM memory; and
    • Standard PC-compatible communication and control ports.
  • Eye-RIS_v2.0 Coprocessor. This coprocessor will be optimized to perform complex real-time image-processing algorithms over high-resolution images at video rates. It will achieve a computing power in the order of 400 GOps. Its architecture includes:

    • Very high-speed standard video input for efficient interfacing with high-resolution off-chip image sensors,
    • A sensor-less ACE-like early-processor with medium resolution for high-speed windowed or tiled applications.
    • A 32bit high-performance RISC digital microprocessor for image post-processing and system control,
    • A DMA controller for efficient data transfer between memory and early/post-processing units,
    • Embedded SRAM memory, and
    • Standard PC-compatible communication and control peripherals.

Subsequent steps in the AnaFocus roadmap include the development of customized, application-specific versions of the Eye-RIS vision systems and their associated hardware-software OEM development kits. Three different platforms are expected to become available during 2006. These platforms will be oriented to active-security automotive systems, intelligent security cameras and low-cost consumer applications.

Q-Eye - QCIF CMOS Smart Image Sensor

GS1010 Microcontroller (uC) - Soc for Wi-Fi Sensors with Years of Battery Life

  • IEEE® 802.11b/g radio
  • 2X ARM7® 32-bit microcontrollers
  • Flash and SRAM memories
  • Multiple I/Os
  • Ultra Low Power

IP Catalogue

Analog-to-Digital Converters 16-bit to 24-bit sigma-delta data converters for precision measurements, high-quality audio and speech applications and broadband xDSL, 10-bit to 12-bit high-speed pipeline for video, imaging and communications and 15-bit low power successive incremental converter for sensor applications.

Digital-to-Analog Converters

Analog Front-ends and Codecs 16-bit to 24-bit sigma-delta analog front-ends and CODECS for precision measurements, high-quality audio and speech applications, 10-bit to 12-bit high-speed pipelined analog front-end for video, imaging and communications.

Portable Power Application DC/DC Converter

  • Step-Down DC/DC Converter
  • Step-Up DC/DC Converter
  • Inverting DC/DC Converter
  • Charge-Pump Converter

High Power Application DC/DC Converter

  • Multiple-Output DC/DC Converter
  • Universal Applications


  • DDR Regulator
  • Negative Voltage Regulator
  • Ultra Low Dropout Linear Regulator
  • Low Dropout Linear Regulator
  • Voltage Reference


  • NiMH/ NiCd Battery Charger
  • Li-Ion Battery Protection


  • Universal Power Switch
  • USB Power Switch



AZM extensive experience in RF & MMIC ASIC design, manufacture and test covers a wide range of applications. Below are examples of previous designs. Please contact us for information regarding your specific requirements.

TRX Front Ends:

  • 100 MHz to 2.5 GHz (VHF, Cellular, ISM)
  • Various modulation schemes including GMSK
  • 2.7 - 5.5V with sleep mode
  • Frequency agile architectures
  • On-chip inductors
  • On-chip PLLs


  • Entire 1.6 GHz receiver frontend
  • On-chip PLL, 2.5-5.5V, sleep mode
  • Dual and single conversion architecture


  • Single or multiple (up to four) on-chip PLLs
  • 50 MHz to 2.2 GHz
  • Digital and analog versions

IR/RF Links:

  • RF links to 2.4 GHz
  • 1.2V TX and 2.7-5.5V RX for pen-based computer
  • On-chip PLL, Filters, A/D, State machines, AGC, Timers, Power rectifiers, Modulators, Demodulators

Optical Fiber:

  • Mux/Demux, TIA, Coder/Decoder, Data Separator, Serial to Parallel Converter, Laser Driver, Multi-channel architectures
  • PECL, ECL and CMOS compatible I/O


  • RF


  • 300+ MHz clock
  • Timing generators, Deskew, FIFO, SRAM
  • Pin electronics

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